This invention relates generally to holographic memories. More particularly, it relates to methods and apparatus for implementing a content addressable holographic memory.
Traditionally, computers have utilized location addressable memory devices. Location addressable memories are accessed by specifying an address for a memory location where data is stored. Such memory devices have included semiconductor memories, magnetic tapes and disks, and optical disks. As computers have become more powerful, both the storage capacity of memory devices and the speed increased. Nevertheless, a limiting factor with respect to the speed at which a computer can operate remains the time that is required to access data stored in memory.
One factor that renders location addressable memories inherently slow is that each location must be accessed individually. This inherent slowness of traditional memories is even more apparent during computations that require database sorting or searching. Such sorting and searching applications become even more time consuming as the size of the database becomes increasingly large.
Designers use various approaches to minimize the long search times associated with location addressable memories. One approach is to utilize search algorithms, such as hash coding, that minimize the number of comparisons that need be performed. Another approach is to utilize hardware architectures, such as pipelining, that enable multiple comparisons to take place simultaneously. However, as the processing speed of computers has increased, these approaches have become ineffective.
The disadvantages of traditional memories are most apparent in modern parallel processing computers. Parallel processing computers employ multiple processor units and exploit application parallelisms to decrease their execution time. Since location addressable memories are accessed serially, those memories create serious data flow bottlenecks in computers which utilize massively parallel architectures.
Content addressable memories (CAMs) have developed in response to this problem. In a CAM, data is accessed based on the data itself, as opposed to the address corresponding to its storage location. In a CAM based system, as in a traditional system, the processor presents a search argument to the CAM. However, unlike a traditional memory, the CAM simultaneously compares the search argument with the contents of a plurality of storage locations in the CAM. Upon identifying a match, the CAM couples the matching data to the processor. Theoretically, such a system reduces any number of comparisons down to one comparison. Consequently, the time to locate any particular search argument is independent of the size of the database being searched. However, in reality CAM based systems suffer from several problems.
In some conventional memory systems, the memory to be searched is read into a processor thus, placing practical limitations on the size of the memory which can be searched simultaneously. In other prior art systems, the processor accesses the memory by way of a pre-defined index of key words and phrases. This is done to reduce the input/output bandwidth requirements of the memory. Consequently, either the memory must have an extremely large bandwidth, or searches can only be performed using a limited set of key words.
Disadvantages of existing CAMs are that they are expensive to build and have substantially lower storage density than do location addressable memories. This results from the overhead circuitry required to perform comparisons, manipulations, and output selection.
Consequently, one object of the present invention is to provide a content addressable memory system which eliminates the need to read the contents of the memory into a digital data processor prior to being able to search the memory.
An additional object of the invention is to provide a content addressable memory system having an improved storage capacity.
Another object of the invention is to provide a content addressable memory system with improved access time while reducing the input/output bandwidth requirements of the memory.
A further object of the invention is to provide a content addressable memory system wherein the memory is addressable without using a previously prepared index of key words and phrases.
An additional object is to provide a content addressable memory system having a relatively inexpensive cost per on-line megabyte of memory.
Other general and specific objects of the invention will in part be obvious and will in part appear hereinafter.